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• Electrical engineer to design VHDL logic circuits for use in aerospace avionics applications.
• Requires BSEE and 5 years of experience in VHDL logic design, or MSEE and 3 years of experience.
• Familiarity with the following is required:
• Serial communication protocols: UART, SPI, I2C, 1-Wire, Ethernet, (SpaceWire familiarity preferred),
• Fixed point mathematical fundamentals, Static Timing Analysis and Timing Closure (setup and hold, slack, skew, etc.),
• Asynchronous Clock Domain crossing and general metastability mitigation techniques,
• Test-bench development, including timing accurate bus functional models, complete functional coverage, etc.
• Experience with generating design documents including specifications, user’s manuals and test plans.
• Physical testing experience including lab measurements (oscilloscope, digital logic analyzer), defining test setups, in-circuit debugging, etc.
• Must be capable of understanding and adhering to department design standards.
• Prefer candidates with ability to work in an Agile project format, team based environment, including Jira and Git environments.
• ModelSim or QuestaSim experience is preferred.