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Job Details

Job Title
: FPGA Verification Engineer
Required Skills
: ASIC, ASIC Physical Designer, AXI, debugging, FPGA, OSVVM, Verification, VHDL
: 12 months

Job Description

On-site with Hybrid possibility.

Required Skills:

• FPGA verification engineer with at least 5 years of VHDL verification and validation experience to verify VHDL logic for use in aerospace avionics applications.
• Requires BSEE with at least 5 years of related work experience or MSEE with at least 3 years of related work experience
• Must have proven records of VHDL design verification and validation.
• Knowledge of formal verification techniques for VHDL is required.
• Must work well on a small team of VHDL design and verification engineers
• Must understand the concept of constrained random verification and functional coverage
• Be able to write Bus Functional Models BFMs in VHDL
• Must be capable of understanding and adhering to department design and verification standards.
• Must be familiar with lab testing including lab measurements (oscilloscope, digital logic analyzer), defining test setups, in-circuit debugging.
• Familiarity with AMBA AXI and APB is highly desirable.
• Familiarity with space fiber and/or space wire is highly desirable.
• Familiarity with agile project format is highly desirable.
• VHDL design experience is highly desirable
• Familiarity with OSVVM ( Open Source VHDL Verification Methodology ) is desirable but will consider candidates with strong VHDL design experience.

Required Details

: 5 years
Travel Required
: No
Clearance Required
: No

Contact Details

Contact person
: Anil Kumar
: 678-203-2570

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