Shift Timings: 9/80 Schedule

• Client is seeking an Advanced Verification Engineer to join our team of highly qualified, diverse individuals in Digital Technology. Qualified applicant will become part of the Digital Technology department, which specializes in product designs for a variety of applications from undersea to outer space.

Roles and Responsibilities:

• The individual will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog and Cadence Xcelium simulation tool. This task includes but not limited to development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc.
• This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.

Basic Qualifications:

• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline
• 9+ years of design verification experience
• Expertise in HDL (VHDL/Verilog) and HVL (SystemVerilog)
• Experience with SystemVerilog Assertions (SVA)
• Advanced knowledge of UVM and SystemVerilog
• Experience with a coverage-driven verification methodology from planning through closure
• Knowledge of industry standard interfaces
• Experience with object oriented programming languages and concepts
• Be able to work in teams and communicate clearly across various levels of engineers
• Proficiency in scripting languages such as Tcl, Python or Perl
• U.S. citizenship is required for all positions