All-In-One Scriptless Test Automation Solution!
• Digital Verification Engineer to support and contribute to a set of test benches to test the unit, payload, IP and Digital designs for the program. The test benches may be based on directed, UVM and/or constrained random technologies.
• The Digital verification engineer will also help implement verification components to be shared across multiple project test benches, develop, and improve VNV/VCRM verification plans, aid in lab/hardware simulation correlation root cause and debug.
• They will implement and execute upon a developed verification plan, drive functional coverage closure, aid in potential emulation debug, and make continuous recommendations and improvements to the verification effort.